In modern Integrated Circuit (IC) system, the core logic unit is designed to operate with 1.0V (with the 65 nm technology) to obtain a high speed, while the Input/Output (I/O) unit is designed to operate with 3.3V, 2.5V or 1.8V to realize the stabilization. Due to the different operation voltages, a converting circuit is configured between the core logic unit and the I/O unit, so that the voltage of 1.0V can be converted into the voltage of 3.3V. The above converting circuit is also referred as a voltage shifter circuit.
FIG. 1 shows a voltage shifter circuit 10 in the prior art, including: PMOS transistors PG1 and PG2; NMOS transistors NG1 and NG2; and an inverter INV. The PMOS transistors PG1 and PG2 are referred as the pull-up transistors and the NMOS transistors NG1 and NG2 are referred as the pull-down transistors. A high voltage signal is input from an input signal source In as the operation voltage for the core circuit. Particularly, a modulated pulse signal of rectangle wave, ranging from 1.0V to 1.2V, is input from the signal source In. An operation voltage ranging from 2.5V to 3.3V is input from the first voltage source VD for the I/O circuit region.
For example, the signal from the signal source In is at the high voltage of 1.2V and the voltage from the first voltage source VD is at 3.3V When the input signal is at the low voltage of 0V, the NMOS transistors NG1 is turned on and the voltage at ND1 is pulled down to low voltage, and the PMOS transistors PG2 is turned on and the voltage at ND2 is pulled up to high voltage of 3.3V When the input signal changes from the low voltage of 0V to the high voltage of 1.2V, the NMOS transistors NG2 is turned on and the voltage at ND2 is pulled down to low voltage of 0V, and the PMOS transistor PG1 is turned on also. Hence, a competition is generated between the NMOS transistor NG1 and the PMOS transistor PG1. Since the voltage from the first voltage source is 3.3V and the voltage for the NMOS transistors NG1 is 1.2V, with the same area, the current-driven capacity of the NMOS transistors NG1 is less than that of the PMOS transistors PG1. Hence, in order to improve the current-driven capacity of the NMOS transistors NG1 and the capacity for pulling down the voltage of ND1, the size of the NMOS transistors NG1 is increased. However, the parasitic capacitance is increased and the voltage shifting speed is lowed. Since the voltage for the core circuit is 1.0V and the voltage for the I/O circuit is 3.3V in the 90 nm technology, a lager area is required due to the larger voltage difference and hence the voltage shifting speed is further affected. In addition, the duty cycle of the output voltage is difficult to be optimized due the competition between the pull-up circuit and the pull-down circuit.
To solve the above problems, a voltage shifter circuit is disclosed in the prior art, as show in FIG. 2. The voltage shifter circuit includes: a pull-up circuit 100, adapted to pull up the voltage at node A or B to a first voltage V2; a pull-down circuit 200, adapted to pull down the voltage at node A or B to the ground voltage i.e. zero voltage; and at least one assistant pull-up device or switching device, adapted to pull up or pull down the voltage at node A or B. The voltage shifter circuit further includes: an inverter 110, adapted to invert the input signal; and an inverter 120, adapted to invert the input signal at node C and output an inverted signal to node D; and an inverter 130, adapted to invert the signal at node B and output an inverted signal to the output terminal of the voltage shifter circuit.
The pull-up circuit 100 includes PMOS transistors P1 and P2, adapted to pull up the voltages at node A and B respectively. The pull-down circuit 200 includes NMOS transistors N1 and N2, adapted to pull down the voltage at node B. The assistant pull-up device or switching device includes: an NOMS transistor N3 coupled between the source and drain of the PMOS transistor P2. The assistant pull-up device or switching device is added for pulling up the voltage at node A or B to the first voltage V2 quickly. The above voltage shifter circuit may improve the speed for shifting the voltage and may alleviate the problem that the NMOS transistors N1 and N2 are large. However, the problems can not be solved completely. For example, the input signal Input is a rectangle wave and ranges from 0 to 1.0V, and the output signal Output at the output terminal is a rectangle wave and ranges from 0 to 3.3V Because the NMOS transistor N3 and N4 are required to be fabricated as the thick oxide transistor (the drain is connected with 3.3V), the threshold voltage is large (about 0.65V) and the effective voltage (=Vgs−Vth=1.0V−0.65V=0.35V) is small when a voltage ranging from 0 to 1.0V is used to control the NMOS transistors N3 and N4. However, when the size of the NMOS transistor N3 and N4 are increased, the parasitic capacitance is also increased. Especially when the difference between the voltage for the core circuit region and the voltage for the I/O circuit region is large, the speed is further affected. In addition, since the competition between the pull-up circuit 100 and the pull-down circuit 200 still exists, the device is sensitive to the process and the duty cycle is difficult to be controlled. Moreover, a direct current path exists from the first voltage source V2 (about 3.3V) to the ground terminal during the voltage shifting, and the power efficiency is lowed.
U.S. Pat. No. 7,145,363 discloses the information related to the above solution.